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1 copyright ? cirrus logic, inc. 1997 (all rights reserved) cirrus logic, inc. crystal semiconductor products division p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com CS5509 single supply, 16-bit a/d converter features l delta-sigma a/d converter - 16-bit no missing codes - linearity error: 0.0015%fs l differential input - pin selectable unipolar/bipolar ranges - common mode rejection 105 db @ dc 120 db @ 50, 60 hz l either 5 v or 3.3 v digital interface l on-chip self-calibration circuitry l output update rates up to 200/second l ultra low power: 1.7 mw description the CS5509 is a single supply, 16-bit, serial-output cmos a/d converter. the CS5509 uses charge-bal- anced (delta-sigma) techniques to provide a low cost, high resolution measurement at output word rates up to 200 samples per second. the on-chip digital filter offers superior line rejection at 50 hz and 60 hz when the device is operated from a 32.768 khz clock (output word rate = 20 hz.). the CS5509 has on-chip self-calibration circuitry which can be initiated at any time or temperature to ensure minimum offset and full-scale errors. low power, high resolution and small package size make the CS5509 an ideal solution for loop-powered transmitters, panel meters, weigh scales and battery powered instruments. ordering information CS5509-ap -40 to +85 c 16-pin plastic dip CS5509-as -40 to +85 c 16-pin soic i cs ain- vref+ vref- dgnd vd+ sclk sdata drdy cal bp/up conv xin ain+ 7 8 910 12 1 14 15 16 3 6 24 xout 5 13 va+ 11 4th-order delta-sigma modulator digital filter calibration m c serial interface logic osc calibration sram differential mar 95 ds125f1
specifications are subject to change without notice. * refer to the specification definitions immediately following the pin description section. analog characteristics (t a = 25 c; va+ = 5v 10%; vd+ = 3.3v 5%; vref+ = 2.5v, vref- = 0v; f clk = 330khz; bipolar mode; r source = 50 w with a 10nf to gnd at ain; ain- = 2.5v; unless otherwise specified.) (notes 1, 2) parameter* min typ max units accuracy linearity error f clk = 32.768 khz f clk = 165 khz f clk = 247.5 khz f clk = 330 khz - - - - 0.0015 0.0015 0.0015 0.005 0.003 0.003 0.003 0.0125 %fs %fs %fs %fs differential nonlinearity - 0.25 0.5 lsb full scale error (note 3) - 0.25 2 lsb full scale drift (note 4) - 0.5 -lsb unipolar offset (note 3) - 0.5 2 lsb unipolar offset drift (note 4) - 0.5 -lsb bipolar offset (note 3) - 0.25 1 lsb bipolar offset drift (note 4) - 0.25 -lsb noise (referred to output) - 0.16 - lsb rms analog input analog input range: unipolar bipolar (note 5, 6) - - 0 to +2.5 2.5 - - volts volts common mode rejection: dc f clk = 32.768khz 50,60 hz (note 2) - 120 105 - - - db db input capacitance - 15 - pf dc bias current (note 1) - 5 - na power supplies dc power supply currents: i total i analog i digital - - - 360 300 60 450 - - m a m a m a power dissipation (note 7) - 1.7 2.25 mw power supply rejection - 80 - db notes: 1. both source resistance and shunt capacitance are critical in determining the CS5509s source impedance requirements. refer to the text section analog input impedance considerations. 2. specifications guaranteed by design, characterization and/or test. 3. applies after calibration at the temperature of interest. 4. total drift over the specified temperature range since calibration at power-up at 25 c. 5. the input is differential. therefore, gnd signal + common mode voltage va+ . 6. the CS5509 can accept input voltages up to the va+ analog supply. in unipolar mode the CS5509 will output all 1s if the dc input magnitude ((ain+)-(ain-)) exceeds ((vref+)-(vref-)) and will output all 0s if the input becomes more negative than 0 volts. in bipolar mode the CS5509 will output all 1s if the dc input magnitude ((ain+)-(ain-)) exceeds ((vref+)-(vref-)) and will output all 0s if the input becomes more negative in magnitude than -((vref+)-(vref-)). 7. all outputs unloaded. all inputs cmos levels. CS5509 2 ds125f1
dynamic characteristics parameter symbol ratio units modulator sampling frequency f s f clk /2 hz output update rate (conv = 1) f out f clk /1622 hz filter corner frequency f -3db f clk /1928 hz settling time to 1/2 lsb (fs step) t s 1/f out s 5v digital characteristics (t a = 25 c; va+, vd+ = 5v 10%; gnd = 0.) (notes 2, 8) parameter symbol min typ max units high-level input voltage: xin all pins except xin v ih v ih 3.5 2.0 - - - - v v low-level input voltage: xin all pins except xin v il v il - - - - 1.5 0.8 v v high-level output voltage (note 9) v oh (vd+)-1.0 - - v low-level output voltage i out = 1.6ma v ol --0.4v input leakage current i in - 1 10 m a 3-state leakage current i oz -- 10 m a digital output pin capacitance c out -9-pf notes: 8. all measurements are performed under static conditions. 9. i out = -100 m a. this guarantees the ability to drive one ttl load. (v oh = 2.4v @ i out = -40 m a). 3.3v digital characteristics (t a = 25 c; va+ = 5v 10%; vd+ = 3.3v 5%; gnd = 0.) (notes 2, 8) parameter symbol min typ max units high-level input voltage: xin all pins except xin v ih v ih 0.7vd+ 0.6vd+ - - - - v v low-level input voltage: xin all pins except xin v il v il - - - - 0.3vd+ 0.16vd+ v v high-level output voltage i out = -400 m a v oh (vd+)-0.3 - - v low-level output voltage i out = 400 m a v ol --0.3v input leakage current i in - 1 10 m a 3-state leakage current i oz -- 10 m a digital output pin capacitance c out -9-pf CS5509 ds125f1 3
5v switching characteristics (t a = 25 c; va+, vd+ = 5v 10%; input levels: logic 0 = 0v, logic 1 = vd+; c l = 50 pf.) (note 2) parameter symbol min typ max units master clock frequency internal oscillator: external clock: xin f clk 30.0 30 32.768 - 53.0 330 khz khz master clock duty cycle 40 - 60 % rise times: any digital input (note 10) any digital output t rise - - - 50 1.0 - m s ns fall times: any digital input (note 10) any digital output t fall - - - 20 1.0 - m s ns start-up power-on reset period (note 11) t res -10-ms oscillator start-up time xtal=32.768 khz (note 12) t osu - 500 - ms wake-up period (note 13) t wup - 1800/f clk -s calibration conv pulse width (cal=1) (note 14) t ccw 100 - - ns conv and cal high to start of calibration t scl --2/f clk +200 ns start of calibration to end of calibration t cal - 3246/f clk -s conversion conv pulse width t cpw 100 - - ns conv high to start of conversion t scn --2/f clk +200 ns set up time bp/up stable prior to drdy falling t bus 82/f clk --s hold time bp/up stable after drdy falls t buh 0- -ns start of conversion to end of conversion (note 15) t con - 1624/f clk - s notes: 10. specified using 10% and 90% points on waveform of interest. 11. an internal power-on-reset is activated whenever power is applied to the device. 12. oscillator start-up time varies with the crystal parameters. this specification does not apply when using an external clock source. 13. the wake-up period begins once the oscillator starts; or when using an external f clk , after the power-on reset time elapses. 14. calibration can also be initiated by pulsing cal high while conv=1. 15. conversion time will be 1622/f clk if conv remains high continuously. CS5509 4 ds125f1
3.3v switching characteristics (t a = 25 c; va+ = 5v 10%; vd+ = 3.3v 5%; input levels: logic 0 = 0v, logic 1 = vd+; c l = 50 pf.) (note 2) parameter symbol min typ max units master clock frequency internal oscillator: external clock: xin f clk 30.0 30 32.768 - 53.0 330 khz khz master clock duty cycle 40 - 60 % rise times: any digital input (note 10) any digital output t rise - - - 50 1.0 - m s ns fall times: any digital input (note 10) any digital output t fall - - - 20 1.0 - m s ns start-up power-on reset period (note 11) t res -10-ms oscillator start-up time xtal=32.768 khz (note 12) t osu - 500 - ms wake-up period (note 13) t wup - 1800/f clk -s calibration conv pulse width (cal=1) (note 14) t ccw 100 - - ns conv and cal high to start of calibration t scl --2/f clk +200 ns start of calibration to end of calibration t cal - 3246/f clk -s conversion conv pulse width t cpw 100 - - ns conv high to start of conversion t scn --2/f clk +200 ns set up time bp/up stable prior to drdy falling t bus 82/f clk --s hold time bp/up stable after drdy falls t buh 0- -ns start of conversion to end of conversion (note 15) t con - 1624/f clk - s CS5509 ds125f1 5
t ccw xin calibration standby standby t scl t cal xin/2 state cal conv figure 1. calibration timing (not to scale) xin xin/2 t buh conversion standby standby conv state t scn t con drdy bp/up t bus t cpw figure 2. conversion timing (not to scale) CS5509 6 ds125f1
3.3v switching characteristics (t a = 25 c; va+ = 5v 10%, vd+ = 3.3v 5%; input levels : logic 0 = 0v, logic 1 = vd+; c l = 50pf.) (note 2) parameter symbol min typ max units serial clock f sclk 0 - 1.25 mhz serial clock pulse width high pulse width low t ph t pl 200 200 - - - - ns ns access time: cs low to data valid (note 16) t csd - 100 200 ns maximum delay time: sclk falling to new sdata bit (note 17) t dd - 400 600 ns output float delay cs high to output hi-z (note 18) sclk falling to hi-z t fd1 t fd2 - - 70 320 150 500 ns ns 5v switching characteristics (t a = 25 c; va+, vd+ = 5v 10%; input levels: logic 0 = 0v, logic 1 = vd+; c l = 50 pf.) (note 2) parameter symbol min typ max units serial clock f sclk 0-2.5mhz serial clock pulse width high pulse width low t ph t pl 200 200 - - - - ns ns access time: cs low to data valid (note 16) t csd - 60 200 ns maximum delay time: sclk falling to new sdata bit (note 17) t dd - 150 310 ns output float delay cs high to output hi-z (note 18) sclk falling to hi-z t fd1 t fd2 - - 60 160 150 300 ns ns notes: 16. if cs is activated asynchronously to drdy, cs will not be recognized if it occurs when drdy is high for 2 clock cycles. the propagation delay time may be as great as 2 f clk cycles plus 200 ns. to guarantee proper clocking of sdata when using asynchronous cs, sclk(i) should not be taken high sooner than 2 f clk + 200 ns after cs goes low. 17. sdata transitions on the falling edge of sclk. note that a rising sclk must occur to enable the serial port shifting mechanism before falling edges can be recognized. 18. if cs is returned high before all data bits are output, the sdata output will complete the current data bit and then go to high impedance. CS5509 ds125f1 7
sclk(i) msb-1 msb msb-2 sdata(o) hi-z msb-1 msb lsb+2 lsb+1 lsb sclk(i) sdata(o) hi-z t fd1 t csd t dd t ph t pl t dd t csd cs cs drdy drdy t fd2 figure 3. timing relationships (not to scale) CS5509 8 ds125f1
recommended operating conditions (dgnd = 0v) (note 19) parameter symbol min typ max units dc power supplies: positive digital positive analog vd+ va+ 3.15 4.5 5.0 5.0 5.5 5.5 v v analog reference voltage (note 20) (vref+)-(vref-) 1.0 2.5 3.6 v analog input voltage: (note 6) unipolar bipolar vain vain 0 -((vref+)-(vref-)) - - (vref+)-(vref-) (vref+)-(vref-) v v notes: 19. all voltages with respect to ground. 20. the CS5509 can be operated with a reference voltage as low as 100 mv; but with a corresponding reduction in noise-free resolution. the common mode voltage of the voltage reference may be any value as long as +vref and -vref remain inside the supply values of va+ and gnd. absolute maximum ratings* parameter symbol min typ max units dc power supplies: ground (note 21) positive digital (note 22) positive analog gnd vd+ va+ -0.3 -0.3 -0.3 - - - (vd+)-0.3 6.0 6.0 v v v input current, any pin except supplies (notes 23 & 24) i in -- 10 ma output current i out -- 25 ma power dissipation (total) (note 25) - - 500 mw analog input voltage ain and vref pins v ina -0.3 - (va+)+0.3 v digital input voltage v ind -0.3 - (vd+)+0.3 v ambient operating temperature t a -40 - 85 c storage temperature t stg -65 - 150 c notes: 21. no pin should go more positive than (va+)+0.3v. 22. vd+ must always be less than (va+)+0.3v, and can never exceed +6.0 v. 23. applies to all pins including continuous overvoltage conditions at the analog input (ain) pin. 24. transient currents of up to 100ma will not cause scr latch-up. maximum input current for a power supply pin is 50 ma. 25. total power dissipation, including all input currents and output currents. * warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. CS5509 ds125f1 9
general description the CS5509 is a low power, 16-bit, monolithic cmos a/d converter designed specifically for measurement of dc signals. the CS5509 in- cludes a delta-sigma charge-balance converter, a voltage reference, a calibration microcontroller with sram, a digital filter and a serial interface. the CS5509 is optimized to operate from a 32.768 khz crystal but can be driven by an ex- ternal clock whose frequency is between 30 khz and 330 khz. when the digital filter is operated with a 32.768 khz clock, the filter has zeros pre- cisely at 50 and 60 hz line frequencies and multiples thereof. the CS5509 uses a "start convert" command to start a convolution cycle on the digital filter. once the filter cycle is completed, the output port is updated. when operated with a 32.768 khz clock the adc converts and updates its output port at 20 samples/sec. the output port operates in a synchronous externally-clocked in- terface format. theory of operation basic converter operation the CS5509 a/d converter has three operating states. these are stand-by, calibration, and con- version. when power is first applied, an internal power-on reset delay of about 10 ms resets all of the logic in the device. the oscillator must then begin oscillating before the device can be con- sidered functional. after the power-on reset is applied, the device enters the wake-up period for 1800 clock cycles after clock is present. this allows the delta-sigma modulator and other cir- cuitry (which are operating with very low currents) to reach a stable bias condition prior to entering into either the calibration or conversion states. during the 1800 cycle wake-up period, the device can accept an input command. execu- tion of this command will not occur until the complete wake-up period elapses. if no com- mand is given, the device enters the standby state. calibration after the initial application of power, the CS5509 must enter the calibration state prior to performing accurate conversions. during calibra- tion, the chip executes a two-step process. the device first performs an offset calibration and then follows this with a gain calibration. the two calibration steps determine the zero refer- ence point and the full scale reference point of the converters transfer function. from these points it calibrates the zero point and a gain slope to be used to properly scale the output digital codes when doing conversions. the calibration state is entered whenever the cal and conv pins are high at the same time. the state of the cal and conv pins at power- on are recognized as commands, but will not be executed until the end of the 1800 clock cycle wake-up period. if cal and conv become active (high) during the 1800 clock cycle wake-up time, the con- verter will wait until the wake-up period elapses before executing the calibration. if the wake-up time has elapsed, the converter will be in the standby mode waiting for instruction and will enter the calibration cycle immediately if cal and conv become active. the calibration lasts for 3246 clock cycles. calibration coefficients are then retained in the sram (static ram) for use during conversion. the state of bp/ up is ignored during calibration but should remain stable throughout the calibra- tion period to minimize noise. when conversions are performed in unipolar mode or in bipolar mode, the converter uses the same calibration factors to compute the digital CS5509 10 ds125f1
output code. the only difference is that in bipo- lar mode the on-chip microcontroller offsets the computed output word by a code value of 8000h. this means that the bipolar measure- ment range is not calibrated from full scale positive to full scale negative. instead it is cali- brated from the bipolar zero scale point to full scale positive. the slope factor is then extended below bipolar zero to accommodate the negative input signals. the converter can be used to con- vert both unipolar and bipolar signals by changing the bp/ up pin. recalibration is not re- quired when switching between unipolar and bipolar modes. at the end of the calibration cycle, the on-chip microcontroller checks the logic state of the conv signal. if the conv input is low the de- vice will enter the standby mode where it waits for further instruction. if the conv signal is high at the end of the calibration cycle, the con- verter will enter the conversion state and perform a conversion on the input channel. the cal signal can be returned low any time after calibration is initiated. conv can also be re- turned low, but it should never be taken low and then taken back high until the calibration period has ended and the converter is in the standby state. if conv is taken low and then high again with cal high while the converter is cali- brating, the device will interrupt the current calibration cycle and start a new one. if cal is taken low and conv is taken low and then high during calibration, the calibration cycle will continue as the conversion command is disre- garded. the state of bp/ up is not important during calibrations. if an "end of calibration" signal is desired, pulse the cal signal high while leaving the conv signal high continuously. once the calibration is completed, a conversion will be performed. at the end of the conversion, drdy will fall to in- dicate the first valid conversion after the calibration has been completed. conversion the conversion state can be entered at the end of the calibration cycle, or whenever the converter is idle in the standby mode. if conv is taken high to initiate a calibration cycle ( cal also high), and remains high until the calibration cy- cle is completed (cal is taken low after conv transitions high), the converter will begin a con- version upon completion of the calibration period. the bp/ up pin is not a latched input. the bp/ up pin controls how the output word from the digital filter is processed. in bipolar mode the output word computed by the digital filter is offset by 8000h (see understanding converter calibration). bp/ up can be changed after a con- version is started as long as it is stable for 82 clock cycles of the conversion period prior to drdy falling. if one wishes to intermix meas- urement of bipolar and unipolar signals on various input signals, it is best to switch the bp/ up pin immediately after drdy falls and leave bp/ up stable until drdy falls again. the digital filter in the CS5509 has a finite im- pulse response and is designed to settle to full accuracy in one conversion time. if conv is left high, the CS5509 will perform continuous conversions. the conversion time will be 1622 clock cycles. if conversion is initi- ated from the standby state, there may be up to two xin clock cycles of uncertainty as to when conversion actually begins. this is because the internal logic operates at one half the external clock rate and the exact phase of the internal clock may be 180 out of phase relative to the xin clock. when a new conversion is initiated from the standby state, it will take up to two xin clock cycles to begin. actual conversion will use 1624 clock cycles before drdy goes low to indicate that the serial port has been up- dated. see the serial interface logic section of CS5509 ds125f1 11
the data sheet for information on reading data from the serial port. in the event the a/d conversion command (conv going positive) is issued during the con- version state, the current conversion will be terminated and a new conversion will be initi- ated. voltage reference the CS5509 uses a differential voltage reference input. the positive input is vref+ and the negative input is vref-. the voltage between vref+ and vref- can range from 1 volt mini- mum to 3.6 volts maximum. the gain slope will track changes in the reference without recalibra- tion, accommodating ratiometric applications. analog input range the analog input range is set by the magnitude of the voltage between the vref+ and vref- pins. in unipolar mode the input range will equal the magnitude of the voltage reference. in bipolar mode the input voltage range will equate to plus and minus the magnitude of the voltage reference. while the voltage reference can be as great as 3.6 volts, its common mode voltage can be any value as long as the reference inputs vref+ and vref- stay within the supply volt- ages va+ and gnd. the differential input voltage can also have any common mode value as long as the maximum signal magnitude stays within the supply voltages. the a/d converter is intended to measure dc or low frequency inputs. it is designed to yield ac- curate conversions even with noise exceeding the input voltage range as long as the spectral components of this noise will be filtered out by the digital filter. for example, with a 3.0 volt reference in unipolar mode, the converter will accurately convert an input dc signal up to 3.0 volts with up to 15% overrange for 60 hz noise. a 3.0 volt dc signal could have a 60 hz component which is 0.5 volts above the maxi- mum input of 3.0 (3.5 volts peak; 3.0 volts dc plus 0.5 volts peak noise) and still accurately convert the input signal (xin = 32.768 khz). this assumes that the signal plus noise ampli- tude stays within the supply voltages. the CS5509 converters output data in binary format when converting unipolar signals and in offset binary format when converting bipolar signals. table 1 outlines the output coding for both unipolar and bipolar measurement modes. converter performance the CS5509 a/d converter has excellent linear- ity performance. calibration minimizes the errors in offset and gain. the CS5509 device has no missing code performance to 16-bits. figure 4 illustrates the dnl of the CS5509. the converter achieves common mode rejection (cmr) at dc of 105 db typical, and cmr at 50 and 60 hz of 120 db typical. the CS5509 can experience some drift as tem- perature changes. the CS5509 uses chopper-stabilized techniques to minimize drift. measurement errors due to offset or gain drift can be eliminated at any time by recalibrating the converter. unipolar input voltage output codes bipolar input voltage >(vref - 1.5 lsb) ffff >(vref - 1.5 lsb) vref - 1.5 lsb ffff fffe vref - 1.5 lsb vref/2 - 0.5 lsb 8000 7fff -0.5 lsb +0.5 lsb 0001 0000 -vref +0.5 lsb <(+0.5 lsb) 0000 <(-vref +0.5 lsb) note: table excludes common mode voltage on the signal and reference inputs. table 1. output coding CS5509 12 ds125f1
analog input impedance considerations the analog input of the CS5509 can be modeled as illustrated in figure 5. capacitors (15 pf each) are used to dynamically sample each of the inputs (ain+ and ain-). every half xin cy- cle the switch alternately connects the capacitor to the output of the buffer and then directly to the ain pin. whenever the sample capacitor is switched from the output of the buffer to the ain pin, a small packet of charge (a dynamic demand of current) is required from the input source to settle the voltage of the sample capaci- tor to its final value. the voltage on the output of the buffer may differ up to 100 mv from the actual input voltage due to the offset voltage of the buffer. timing allows one half of a xin clock cycle for the voltage on the sample capaci- tor to settle to its final value. an equation for the maximum acceptable source resistance is derived. rs max = - 1 2xin ( 15pf + c ext ) ln ? v e v e + 15pf ( 100mv ) ( 15pf + c ext ? this equation assumes that the offset voltage of the buffer is 100 mv, which is the worst case. the value of ve is the maximum error voltage which is acceptable. c ext is the combination of any external or stray capacitance. for a maximum error voltage (ve) of 10 m v in the CS5509 (1/4lsb at 16-bits), the above equa- tion indicates that when operating from a 32.768 khz xin, source resistances up to 110 k w are acceptable in the absence of external capacitance (c ext = 0). the vref+ and vref- inputs have nearly the same structure as the ain+ and ain- inputs. therefore, the discussion on analog input imped- ance applies to the voltage reference inputs as well. 0 65,535 codes 32,768 dnl (lsb) +1 0 -1 +1/2 -1/2 figure 4. CS5509 differential nonlinearity plot. + 15 pf v os 100 mv + v os 100 mv internal bias voltage 15 pf ain+ ain- - - figure 5. analog input model CS5509 ds125f1 13
digital filter characteristics the digital filter in the CS5509 is the combina- tion of a comb filter and a low pass filter. the comb filter has zeros in its transfer function which are optimally placed to reject line interfer- ence frequencies (50 and 60 hz and their multiples) when the CS5509 is clocked at 32.768 khz. figures 6, 7 and 8 illustrate the magnitude and phase characteristics of the filter. figure 6 illustrates the filter attenuation from dc to 260 hz. at exactly 50, 60, 100, and 120 hz the filter provides over 120 db of rejection. ta- ble 2 indicates the filter attenuation for each of the potential line interference frequencies when the converter is operating with a 32.768 khz clock. the converter yields excellent attenuation of these interference frequencies even if the fun- damental line frequency should vary 1% from 0 0 40 402.83 80 805.66 120 1208.5 160 1611.3 200 2014.2 240 2416.9 frequency (hz) -160 -140 -120 -100 -80 -60 -40 -20 0 attenuation (db) xin = 32.768 khz x1 x2 x1 = 32.768khz x2 = 330.00khz figure 6. filter magnitude plot to 260 hz frequency notch frequency minimum (hz) depth (hz) attenuation (db) (db ) 50 125.6 50 1% 55.5 60 126.7 60 1% 58.4 100 145.7 100 1% 62.2 120 136.0 120 1% 68.4 150 118.4 150 1% 74.9 180 132.9 180 1% 87.9 200 102.5 200 1% 94.0 240 108.4 240 1% 104.4 table 2. filter notch attenuation (xin = 32.768 khz) 0 5 10 15 20 25 30 35 40 45 50 frequency (hz) -140 -120 -100 -80 -60 -40 -20 0 attenuation (db) flatness db -0.010 -0.041 -0.093 -0.166 -0.259 -0.510 -0.667 -0.846 -1.047 -3.093 1 2 3 4 5 6 7 8 9 10 17 xin = 32.768 khz frequency -0.374 figure 7. filter magnitude plot to 50 hz 0 5 10 15 20 25 30 35 40 45 50 frequency (hz) -180 -135 -90 -45 0 45 90 135 180 phase (degrees) xin = 32.768 khz figure 8. filter phase plot to 50 hz CS5509 14 ds125f1
its specified frequency. the -3db corner fre- quency of the filter when operating from a 32.768 khz clock is 17 hz. figure 8 illustrates that the phase characteristics of the filter are pre- cisely linear phase. if the CS5509 is operated at a clock rate other than 32.768 khz, the filter characteristics, in- cluding the comb filter zeros, will scale with the operating clock frequency. therefore, optimum rejection of line frequency interference will oc- cur with the CS5509 running at 32.768 khz. anti-alias considerations for spectral measurement applications input frequencies greater than one half the out- put word rate (conv = 1) may be aliased by the converter. to prevent this, input signals should be limited in frequency to no greater than one half the output word rate of the converter (when conv =1). frequencies close to the modulator sample rate (xin/2) and multiples thereof may also be aliased. if the signal source includes spectral components above one half the output word rate (when conv = 1) these components should be removed by means of low-pass filter- ing prior to the a/d input to prevent aliasing. spectral components greater than one half the output word rate on the vref inputs (vref+ and vref-) may also be aliased. filtering of the reference voltage to remove these spectral com- ponents from the reference voltage is desirable. crystal oscillator the CS5509 is designed to be operated using a 32.768 khz "tuning fork" type crystal. one end of the crystal should be connected to the xin input. the other end should be attached to xout. short lead lengths should be used to minimize stray capacitance. over the industrial temperature range (-40 to +85 c) the on-chip gate oscillator will oscillate with other crystals in the range of 30 khz to 53 khz. the chip will operate with external clock frequencies from 30 khz to 330 khz over the in- dustrial temperature range. the 32.768 khz crystal is normally specified as a time-keeping crystal with tight specifications for both initial frequency and for drift over temperature. to maintain excellent frequency stability, these crystals are specified only over limited operating temperature ranges (i.e. -10 c to +60 c) by the manufacturers. applications of these crystals with the CS5509 does not require tight initial tolerance or low tempco drift. therefore, a lower cost crystal with looser initial tolerance and tem- pco will generally be adequate for use with the CS5509. also check with the manufacturer about wide temperature range application of their standard crystals. generally, even those crystals specified for limited temperature range will operate over much larger ranges if fre- quency stability over temperature is not a requirement. the frequency stability can be as bad as 3000 ppm over the operating tempera- ture range and still be typically better than the line frequency (50 hz or 60 hz) stability over cycle-to-cycle during the course of a day. serial interface logic the digital filter in the CS5509 takes 1624 clock cycles to compute an output word once a con- version begins. at the end of the conversion cycle, the filter will attempt to update the serial port. two clock cycles prior to the update drdy will go high. when drdy goes high just prior to a port update it checks to see if the port is either empty or unselected ( cs = 1). if the port is empty or unselected, the digital filter will update the port with a new output word. when new data is put into the port drdy will go low. CS5509 ds125f1 15
reading serial data sdata is the output pin for the serial data. when cs goes low after new data becomes available ( drdy goes low), the sdata pin comes out of hi-z with the msb data bit pre- sent. sclk is the input pin for the serial clock. if the msb data bit is on the sdata pin, the first rising edge of sclk enables the shifting mechanism. this allows the falling edges of sclk to shift subsequent data bits out of the port. note that if the msb data bit is output and the sclk signal is high, the first falling edge of sclk will be ignored because the shifting mechanism has not become activated. after the first rising edge of sclk, each subsequent fall- ing edge will shift out the serial data. once the lsb is present, the falling edge of sclk will cause the sdata output to go to hi-z and drdy to return high. the serial port register will be updated with a new data word upon the completion of another conversion if the serial port has been emptied, or if the cs is inactive (high). cs can be operated asynchronously to the drdy signal. the drdy signal need not be monitored as long as the cs signal is taken low for at least two xin clock cycles plus 200 ns prior to sclk being toggled. this ensures that cs has gained control over the serial port. power supplies and grounding the analog and digital supply pins to the CS5509 are brought out on separate pins to minimize noise coupling between the analog and digital sections of the chip. in the digital section of the chip the supply current flows into the vd+ pin and out of the gnd pin. as a cmos device, the CS5509 requires that the supply volt- age on the va+ pin always be more positive than the voltage on any other pin of the device. if this requirement is not met, the device can latch-up or be damaged. in all circumstances the va+ voltage must remain more positive than the vd+ or gnd pins; vd+ must remain more positive than the gnd pin. figure 9a illustrates the system connection dia- gram for the CS5509. note that all supply pins are bypassed with 0.1 m f capacitors and that the vd+ digital supply is derived from the va+ supply. figure 9b illustrates the CS5509 operat- ing from a +5v analog supply and +3.3v digital supply. when using separate supplies for va+ and vd+, va+ must be established first. vd+ should never become more positive than va+ under any operating condition. remember to in- vestigate transient power-up conditions, when one power supply may have a faster rise time. schematic & layout review service confirm optimum schematic & layout before building your board. confirm optimum schematic & layout before building your board. for our free review service call applications engineering. for our free review service call applications engineering. call: (512) 445-7222 CS5509 16 ds125f1
CS5509 +5v analog supply vd+ va+ vref+ vref- gnd 0.1 m f 0.1 m f 8 7 9 10 11 12 13 + - analog signal ain+ ain- sclk sdata 14 15 xin xout 16 drdy cal 3 1 cs conv 2 6 bp/up 4 5 32.768 khz 10 w voltage reference optional clock source serial data interface control logic figure 9a. system connection diagram using a single supply CS5509 ds125f1 17
CS5509 +5v analog supply vd+ va+ vref+ vref- gnd 0.1 m f 0.1 m f 8 7 9 10 11 12 13 + - analog signal ain+ ain- sclk sdata 14 15 xin xout 16 drdy cal 3 1 cs conv 2 6 bp/up 4 5 32.768 khz voltage reference optional clock source serial data interface control logic +3.3v to +5v digital supply note: vd+ must never be more positive than va+ figure 9b. system connection diagram using split supplies CS5509 18 ds125f1
pin descriptions* clock generator xin; xout - crystal in; crystal out, pins 4, 5. a gate inside the chip is connected to these pins and can be used with a crystal to provide the master clock for the device. alternatively, an external (cmos compatible) clock can be supplied into the xin pin to provide the master clock for the device. loss of clock will put the device into a lower powered state (approximately 70% power reduction). serial output i/o cs - chip select, pin 1. this input allows an external device to access the serial port. drdy - data ready, pin 16. data ready goes low at the end of a digital filter convolution cycle to indicate that a new output word has been placed into the serial port. drdy will return high after all data bits are shifted out of the serial port or two master clock cycles before new data becomes available if the cs pin is inactive (high). sdata - serial data output, pin 15. sdata is the output pin of the serial output port. data from this pin will be output at a rate determined by sclk. data is output msb first and advances to the next data bit on the falling edges of sclk. sdata will be in a high impedance state when not transmitting data. sclk - serial clock input, pin 14. a clock signal on this pin determines the output rate of the data from the sdata pin. this pin must not be allowed to float. 8 1 2 3 4 5 6 7 16 15 14 13 12 11 10 9 chip select cs drdy data ready convert conv sdata serial data output calibrate cal sclk serial clock input crystal in xin vd+ positive digital power crystal out xout gnd ground bipolar/unipolar bp/ up va+ positive analog power differential analog input ain+ vref- voltage reference input differential analog input ain- vref+ voltage reference input *pinout applies to both pdip and soic CS5509 ds125f1 19
control input pins cal - calibrate, pin 3. when taken high the same time that the conv pin is taken high the converter will perform a self-calibration which includes calibration of the offset and gain scale factors in the converter. conv - convert, pin 2. the conv pin initiates a calibration cycle if it is taken from low to high while the cal pin is high, or it initiates a conversion if it is taken from low to high with the cal pin low. if conv is held high (cal low) the converter will do continuous conversions. bp/ up - bipolar/unipolar, pin 6. the bp/ up pin selects the conversion mode of the converter. when high the converter will convert bipolar input signals; when low it will convert unipolar input signals. measurement and reference inputs ain+, ain- - differential analog inputs, pins 7, 8. analog differential inputs to the delta-sigma modulator. vref+, vref- - differential voltage reference inputs, pins 9, 10. a differential voltage reference on these pins operates as the voltage reference for the converter. the voltage between these pins can be any voltage between 1.0 and 3.6 volts. power supply connections va+ - positive analog power, pin 11. positive analog supply voltage. nominally +5 volts. vd+ - positive digital power, pin 13. positive digital supply voltage. nominally +5 volts or +3.3 volts. gnd - ground, pin 12. ground. CS5509 20 ds125f1
specification definitions linearity error the deviation of a code from a straight line which connects the two endpoints of the a/d converter transfer function. one endpoint is located 1/2 lsb below the first code transition and the other endpoint is located 1/2 lsb beyond the code transition to all ones. units in percent of full-scale. differential nonlinearity the deviation of a codes width from the ideal width. units in lsbs. full scale error the deviation of the last code transition from the ideal [{(vref+) - (vref-)} - 3 2 lsb]. units are in lsbs. unipolar offset the deviation of the first code transition from the ideal ( 1 2 lsb above the voltage on the ain- pin.) when in unipolar mode (bp/ up low). units are in lsbs. bipolar offset the deviation of the mid-scale transition (011...111 to 100...000) from the ideal ( 1 2 lsb below the voltage on the ain- pin.) when in bipolar mode (bp/ up high). units are in lsbs CS5509 ds125f1 21
appendix the following companies provide 32.768 khz crystals in many package varieties and temperature ranges. fox electronics 5570 enterprise parkway fort meyers, fl 33905 (813) 693-0099 micro crystal division / smh 702 west algonquin road arlington heights, il 60005 (708) 806-1485 saronix 4010 transport street palo alto, california 94303 (415) 856-6900 statek 512 north main orange, california 92668 (714) 639-7810 iqd ltd. north street crewkerne somerset ta18 7ak england 01460 77155 mr. pierre hersberger microcrystal/div. eta s.a. schild-rust-strasse 17 grenchen ch-2540 switzerland 065 53 05 57 taiwan xtal corp. 5f. no. 16, sec 2, chung yang s. rd. reitou, taipei, taiwan r. o. c. tel: 02-894-1202 fax: 02-895-6207 interquip limited 24/f million fortune industrial centre 34-36 chai wan kok street, tsuen wan n t tel: 4135515 fax: 4137053 s& t enterprises, ltd. rm 404 blk b sea view estate north point, hong kong tel: 5784921 fax: 8073126 mr. darren mcleod hy-q international pty. ltd. 12 rosella road, frankson, 3199 victoria, australia tel: 61-3-783 9611 fax: 61-3-783 9703 CS5509 22 ds125f1
23 copyright ? cirrus logic, inc. 1998 (all rights reserved) cirrus logic, inc. crystal semiconductor products division p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com cdb5509 evaluation board for the CS5509 a/d converter features l operation with on-board 32.768 khz crystal or off-board clock source l dip switch selectable: - bp/up mode l on-board precision voltage reference l access to all digital control pins description the cdb5509 is a circuit board designed to provide quick evaluation of the CS5509 a/d converter. the board provides buffered digital signals, an on-board precision voltage reference, options for using an external clock, and a momentary switch to initiate calibration. ordering information cdb5509 evaluation board i ain+ ain- +5v gnd CS5509 clkin vref h e a d e r b u f f e r s mar 95 ds125db1
introduction the cdb5509 evaluation board provides a quick means of testing the CS5509 a/d converter. the CS5509 converter requires a minimal amount of external circuitry. the evaluation board comes configured with the a/d converter chip operat- ing from a 32.768 khz crystal and with an off-chip precision 2.5 volt reference. the board provides access to all of the digital interface pins of the CS5509 chip. evaluation board overview the board provides a complete means of making the CS5509 a/d converter chip function. the user must provide a means of taking the output data from the board in serial format and using it in his system. figure 1 illustrates the schematic for the board. the board comes configured for the a/d con- verter chip to operate from the 32.768 khz watch crystal. a bnc connector for an external clock is provided on the board. to connect the external bnc source to the converter chip, a cir- cuit trace must be cut. then a jumper must be inserted in the proper holes to connect the xin pin of the converter to the input line from the bnc. the bnc input is terminated with a 50 w resistor. remove this resistor if driving from a logic gate. see the schematic in figure 1. the board comes with the a/d converter vref+ and vref- pins hard-wired to the 2.5 volt bandgap voltage reference ic on the board. all of the control pins of the CS5509 are avail- able at the j1 header connector. buffer ics u2 and u3 are used to buffer the converter for inter- face to off-board circuits. the buffers are used on the evaluation board only because the exact loading and off-board circuitry is unknown. most applications will not require the buffer ics for proper operation. to put the board in operation, select either bipo- lar or unipolar mode with dip switch s2. then press the cal pushbutton after the board is powered up. this initiates calibration of the con- verter which is required before measurements can be taken. with conv high (s2-3 open) the converter will convert continuously. figure 3 il- lustrates the cab5509 adapter board. the cab5509 translates a cs5505 pinout to a CS5509 pinout. figures 4 and 5 illustrate the evaluation board layout while figure 6 illustrates the component placement (silkscreen) of the evaluation board. cdb5509 24 ds125db1
figure 1. adc connections u3c r21 47k vd+ u3d 7 8 10 9 tp14 13 11 12 vd+ r16 100k tp13 u3b u3a 56 4 3 1 2 vd+ c18 0.1 m f 14 sclki sclko sdata drdy a1 a0 cs conv cal u2f 8 15 14 u2e 12 11 u2d 10 9 u2c 67 u2b 45 u2a 3 r20 r19 r18 47k r17 47k vd+ vd+ c17 0.1 m f 2 1 tp12 tp11 tp7 tp8 tp9 tp10 r1 100k sclk drdy sdata +5 c16 10 m f r22 10 + j2 j1 r10 20k u2 74hc4050 u3 74hc125 vd+ 100k vd+ 100k r25 100k r24 100k r23 100k s2 a1 a0 conv bp/up bp/up +5 +5 0.01 m f 1a 1b 2a 2b 3a c8 0.1 m f 6 5 4 2 lt1019 -2.5 v +5 c9 0.1 m f external vref + - r8 25k 3b va+ gnd vd+ xin xout bp/up sclk sdata cal conv cs drdy vref+ vref- 9 10 6 14 15 16 1 2 3 10 r9 c10 0.1 m f 11 13 vd+ +5 c7 0.1 m f c11 0.01 m f cal r11 100k 12 y1 32.768 khz r2 r3 50 clkin 45 tp15 200 r4 ain+ 402 ain+ 7 r13 ain- tp6 402 c15 100k 100k r31 r12 r27 r26 c19 c20 1k 1k 10nf 10nf u1 CS5509 +5v gnd c5 +5 + c2 10 m f 0.1 m f d1 6.8v agnd dgnd ain- 8 note: buffers not required for general applications. cdb5509 ds125db1 25
8 1 2 3 4 5 6 7 16 15 14 13 12 11 10 9 cs drdy conv sdata cal sclk xin vd+ xout gnd bp/ up va+ ain+ vref- ain- vref+ figure 2. CS5509 pin layout 1 116 24 89 13 12 (top view) figure 3. cab5509 adapter board cdb5509 26 ds125db1
figure 4. top ground plane layer (not to scale) cdb5509 ds125db1 27
figure 5. bottom trace layer (not to scale) cdb5509 28 ds125db1
figure 6. silk screen layer (not to scale) cdb5509 a a cdb5509 ds125db1 29

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